325 lines
9.8 KiB
Plaintext
325 lines
9.8 KiB
Plaintext
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/*
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* GENERATED FILE - DO NOT EDIT
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* (c) Code Red Technologies Ltd, 2008-2013
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* (c) NXP Semiconductors 2013-2019
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* Generated linker script file for LPC4357
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* Created from linkscript.ldt by FMCreateLinkLibraries
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* Using Freemarker v2.3.23
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* MCUXpresso IDE v10.2.1 [Build 795] [2018-07-25] on May 15, 2019 5:48:43 PM
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*/
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MEMORY
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{
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/* Define each memory region */
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MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
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MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */
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RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
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RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */
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RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */
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RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */
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RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */
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}
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/* Define a symbol for the top of each memory region */
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__base_MFlashA512 = 0x1a000000 ; /* MFlashA512 */
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__base_Flash = 0x1a000000 ; /* Flash */
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__top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */
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__top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */
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__base_MFlashB512 = 0x1b000000 ; /* MFlashB512 */
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__base_Flash2 = 0x1b000000 ; /* Flash2 */
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__top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */
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__top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */
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__base_RamLoc32 = 0x10000000 ; /* RamLoc32 */
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__base_RAM = 0x10000000 ; /* RAM */
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__top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
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__top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
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__base_RamLoc40 = 0x10080000 ; /* RamLoc40 */
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__base_RAM2 = 0x10080000 ; /* RAM2 */
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__top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */
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__top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */
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__base_RamAHB32 = 0x20000000 ; /* RamAHB32 */
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__base_RAM3 = 0x20000000 ; /* RAM3 */
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__top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */
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__top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */
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__base_RamAHB16 = 0x20008000 ; /* RamAHB16 */
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__base_RAM4 = 0x20008000 ; /* RAM4 */
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__top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */
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__top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */
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__base_RamAHB_ETB16 = 0x2000c000 ; /* RamAHB_ETB16 */
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__base_RAM5 = 0x2000c000 ; /* RAM5 */
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__top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */
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__top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */
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ENTRY(ResetISR)
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SECTIONS
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{
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.text_Flash2 : ALIGN(4)
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{
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FILL(0xff)
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*(.text_Flash2*) /* for compatibility with previous releases */
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*(.text_MFlashB512*) /* for compatibility with previous releases */
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*(.text.$Flash2*)
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*(.text.$MFlashB512*)
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*(.rodata.$Flash2*)
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*(.rodata.$MFlashB512*)
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} > MFlashB512
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/* MAIN TEXT SECTION */
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.text : ALIGN(4)
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{
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FILL(0xff)
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__vectors_start__ = ABSOLUTE(.) ;
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KEEP(*(.isr_vector))
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/* Global Section Table */
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. = ALIGN(4) ;
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__section_table_start = .;
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__data_section_table = .;
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LONG(LOADADDR(.data));
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LONG( ADDR(.data));
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LONG( SIZEOF(.data));
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LONG(LOADADDR(.data_RAM2));
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LONG( ADDR(.data_RAM2));
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LONG( SIZEOF(.data_RAM2));
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LONG(LOADADDR(.data_RAM3));
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LONG( ADDR(.data_RAM3));
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LONG( SIZEOF(.data_RAM3));
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LONG(LOADADDR(.data_RAM4));
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LONG( ADDR(.data_RAM4));
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LONG( SIZEOF(.data_RAM4));
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LONG(LOADADDR(.data_RAM5));
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LONG( ADDR(.data_RAM5));
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LONG( SIZEOF(.data_RAM5));
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__data_section_table_end = .;
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__bss_section_table = .;
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LONG( ADDR(.bss));
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LONG( SIZEOF(.bss));
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LONG( ADDR(.bss_RAM2));
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LONG( SIZEOF(.bss_RAM2));
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LONG( ADDR(.bss_RAM3));
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LONG( SIZEOF(.bss_RAM3));
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LONG( ADDR(.bss_RAM4));
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LONG( SIZEOF(.bss_RAM4));
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LONG( ADDR(.bss_RAM5));
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LONG( SIZEOF(.bss_RAM5));
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__bss_section_table_end = .;
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__section_table_end = . ;
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/* End of Global Section Table */
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*(.after_vectors*)
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} > MFlashA512
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.text : ALIGN(4)
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{
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*(.text*)
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*(.rodata .rodata.* .constdata .constdata.*)
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. = ALIGN(4);
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} > MFlashA512
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/*
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* for exception handling/unwind - some Newlib functions (in common
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* with C++ and STDC++) use this.
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*/
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.ARM.extab : ALIGN(4)
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > MFlashA512
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__exidx_start = .;
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.ARM.exidx : ALIGN(4)
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > MFlashA512
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__exidx_end = .;
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_etext = .;
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/* DATA section for RamLoc40 */
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.data_RAM2 : ALIGN(4)
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{
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FILL(0xff)
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PROVIDE(__start_data_RAM2 = .) ;
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*(.ramfunc.$RAM2)
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*(.ramfunc.$RamLoc40)
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*(.data.$RAM2*)
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*(.data.$RamLoc40*)
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. = ALIGN(4) ;
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PROVIDE(__end_data_RAM2 = .) ;
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} > RamLoc40 AT>MFlashA512
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/* DATA section for RamAHB32 */
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.data_RAM3 : ALIGN(4)
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{
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FILL(0xff)
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PROVIDE(__start_data_RAM3 = .) ;
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*(.ramfunc.$RAM3)
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*(.ramfunc.$RamAHB32)
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*(.data.$RAM3*)
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*(.data.$RamAHB32*)
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. = ALIGN(4) ;
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PROVIDE(__end_data_RAM3 = .) ;
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} > RamAHB32 AT>MFlashA512
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/* DATA section for RamAHB16 */
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.data_RAM4 : ALIGN(4)
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{
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FILL(0xff)
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PROVIDE(__start_data_RAM4 = .) ;
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*(.ramfunc.$RAM4)
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*(.ramfunc.$RamAHB16)
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*(.data.$RAM4*)
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*(.data.$RamAHB16*)
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. = ALIGN(4) ;
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PROVIDE(__end_data_RAM4 = .) ;
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} > RamAHB16 AT>MFlashA512
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/* DATA section for RamAHB_ETB16 */
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.data_RAM5 : ALIGN(4)
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{
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FILL(0xff)
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PROVIDE(__start_data_RAM5 = .) ;
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*(.ramfunc.$RAM5)
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*(.ramfunc.$RamAHB_ETB16)
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*(.data.$RAM5*)
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*(.data.$RamAHB_ETB16*)
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. = ALIGN(4) ;
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PROVIDE(__end_data_RAM5 = .) ;
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} > RamAHB_ETB16 AT>MFlashA512
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/* MAIN DATA SECTION */
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.uninit_RESERVED : ALIGN(4)
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{
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KEEP(*(.bss.$RESERVED*))
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. = ALIGN(4) ;
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_end_uninit_RESERVED = .;
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} > RamLoc32
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/* Main DATA section (RamLoc32) */
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.data : ALIGN(4)
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{
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FILL(0xff)
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_data = . ;
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*(vtable)
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*(.ramfunc*)
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*(.data*)
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. = ALIGN(4) ;
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_edata = . ;
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} > RamLoc32 AT>MFlashA512
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/* BSS section for RamLoc40 */
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.bss_RAM2 : ALIGN(4)
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{
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PROVIDE(__start_bss_RAM2 = .) ;
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*(.bss.$RAM2*)
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*(.bss.$RamLoc40*)
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. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
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PROVIDE(__end_bss_RAM2 = .) ;
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} > RamLoc40
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/* BSS section for RamAHB32 */
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.bss_RAM3 : ALIGN(4)
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{
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PROVIDE(__start_bss_RAM3 = .) ;
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*(.bss.$RAM3*)
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*(.bss.$RamAHB32*)
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. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
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PROVIDE(__end_bss_RAM3 = .) ;
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} > RamAHB32
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/* BSS section for RamAHB16 */
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.bss_RAM4 : ALIGN(4)
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{
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PROVIDE(__start_bss_RAM4 = .) ;
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*(.bss.$RAM4*)
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*(.bss.$RamAHB16*)
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. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
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PROVIDE(__end_bss_RAM4 = .) ;
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} > RamAHB16
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/* BSS section for RamAHB_ETB16 */
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.bss_RAM5 : ALIGN(4)
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{
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PROVIDE(__start_bss_RAM5 = .) ;
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*(.bss.$RAM5*)
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*(.bss.$RamAHB_ETB16*)
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. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
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PROVIDE(__end_bss_RAM5 = .) ;
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} > RamAHB_ETB16
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/* MAIN BSS SECTION */
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.bss : ALIGN(4)
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{
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_bss = .;
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*(.bss*)
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*(COMMON)
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. = ALIGN(4) ;
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_ebss = .;
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PROVIDE(end = .);
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} > RamLoc32
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/* NOINIT section for RamLoc40 */
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.noinit_RAM2 (NOLOAD) : ALIGN(4)
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{
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*(.noinit.$RAM2*)
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*(.noinit.$RamLoc40*)
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. = ALIGN(4) ;
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} > RamLoc40
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/* NOINIT section for RamAHB32 */
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.noinit_RAM3 (NOLOAD) : ALIGN(4)
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{
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*(.noinit.$RAM3*)
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*(.noinit.$RamAHB32*)
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. = ALIGN(4) ;
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} > RamAHB32
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/* NOINIT section for RamAHB16 */
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.noinit_RAM4 (NOLOAD) : ALIGN(4)
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{
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*(.noinit.$RAM4*)
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*(.noinit.$RamAHB16*)
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. = ALIGN(4) ;
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} > RamAHB16
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/* NOINIT section for RamAHB_ETB16 */
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.noinit_RAM5 (NOLOAD) : ALIGN(4)
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{
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*(.noinit.$RAM5*)
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*(.noinit.$RamAHB_ETB16*)
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. = ALIGN(4) ;
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} > RamAHB_ETB16
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/* DEFAULT NOINIT SECTION */
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.noinit (NOLOAD): ALIGN(4)
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{
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_noinit = .;
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*(.noinit*)
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. = ALIGN(4) ;
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_end_noinit = .;
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} > RamLoc32
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PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
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PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
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/* ## Create checksum value (used in startup) ## */
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PROVIDE(__valid_user_code_checksum = 0 -
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(_vStackTop
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+ (ResetISR + 1)
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+ (NMI_Handler + 1)
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+ (HardFault_Handler + 1)
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+ (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */
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+ (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */
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+ (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
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) );
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/* Provide basic symbols giving location and size of main text
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* block, including initial values of RW data sections. Note that
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* these will need extending to give a complete picture with
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* complex images (e.g multiple Flash banks).
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*/
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_image_start = LOADADDR(.text);
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_image_end = LOADADDR(.data) + SIZEOF(.data);
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_image_size = _image_end - _image_start;
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}
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